Overview of TGV Architecture
Through-Glass Vias represent a critical interconnection technology in advanced semiconductor packaging, particularly for high-density applications requiring vertical electrical pathways through glass substrates. Unlike traditional printed circuit board (PCB) vias that traverse organic materials, TGVs must navigate the crystalline and amorphous phases of engineered glass-core substrates, creating unique mechanical and thermal challenges. The fundamental architecture consists of a cylindrical conductive channel—typically 50 to 200 micrometers in diameter—that extends completely through a glass substrate layer ranging from 200 to 500 micrometers in thickness.
The glass-core substrate itself is a composite material engineered to provide dimensional stability, thermal conductivity, and electrical insulation properties superior to traditional epoxy-glass laminates. These substrates employ borosilicate or aluminosilicate glass matrices, sometimes reinforced with ceramic particulates, to achieve coefficients of thermal expansion (CTE) in the range of 3 to 6 ppm/K—significantly lower than organic substrates at 15-20 ppm/K. This lower CTE is both advantageous and problematic: advantageous for reducing overall package warpage, but problematic when metallized vias create localized stress concentrations.
Metallization Process Sequences
The creation of functional TGVs involves several sequential metallization stages, each introducing distinct material properties and stress conditions:
Via Hole Formation and Surface Preparation: The initial step involves mechanical or laser drilling to create the cylindrical void through the glass substrate. Laser drilling—particularly using femtosecond or picosecond laser systems—creates thermally affected zones (TAZ) around the via perimeter where the glass undergoes localized recrystallization or microcracking. These subsurface defects, typically 10-50 micrometers deep, become critical stress concentration points during thermal cycling. Subsequent wet chemical cleaning removes debris and creates a hydroxylated glass surface essential for adhesion chemistry.
Seed Layer Deposition: Copper seed layers (typically 1-3 micrometers) are deposited via physical vapor deposition (PVD) or electroless plating. PVD methods create directional coating with potential shadowing effects in high-aspect-ratio vias, while electroless plating provides more uniform coverage but introduces phosphorus-rich intermetallic phases at the copper-glass interface. These seed layers establish the initial mechanical bond between copper and glass—a bond that will be severely tested during thermal cycling.
Electroplating and Via Fill: Copper electroplating fills the via to completion, typically achieving 99.9% density under optimized conditions. However, real-world plating processes often produce columnar grain structures with preferred <100> orientation, creating anisotropic mechanical properties. Additionally, organic additives used in plating chemistry (suppressors, accelerators, levelers) can become trapped as inclusions, particularly at the bottom of the via where mass transport is limited. These inclusions create localized weakness points prone to void formation during subsequent thermal processing.
Annealing and Recrystallization: Post-plating thermal annealing at 250-350°C is employed to relieve plating-induced stress and promote grain growth. However, this thermal excursion creates the first significant CTE mismatch stress event. The copper (CTE ≈ 16.5 ppm/K) expands more than the glass (CTE ≈ 4 ppm/K), generating radial compressive stress in the copper and radial tensile stress at the copper-glass interface. Grain boundary migration during annealing can create Kirkendall voids—nanometer-scale cavities formed by differential atomic diffusion—which nucleate larger voids during subsequent thermal cycling.
Material Interface Chemistry
The copper-glass interface is fundamentally reactive. Even without intentional adhesion promoters, copper atoms diffuse into glass at elevated temperatures, while oxygen from the glass diffuses into copper, forming copper oxide phases. This creates a compositionally graded interface region typically 0.5-2 micrometers thick, containing mixed-valence copper oxides (Cu₂O and CuO) and copper-silicate phases. While these phases improve mechanical adhesion, they also introduce brittleness and act as preferential crack initiation sites.
Modern processes employ chromium or titanium adhesion layers (50-200 nm) to improve interface stability and reduce copper oxidation. However, these layers introduce additional CTE mismatches: chromium exhibits CTE ≈ 4.9 ppm/K (similar to glass), creating a three-layer system with graded stress distribution. The adhesion layer thickness becomes critical—insufficient thickness provides inadequate bonding, while excessive thickness creates stress concentration that paradoxically weakens the interface.